1. Field of the Invention
The present invention relates generally to integrated circuit devices, and more specifically to test equipment for testing such devices.
2. Description of the Prior Art
It is well known in the field of integrated circuit devices that proper testing of devices during and after fabrication is important to improving the reliability and yield of product shipped to customers. Many tests can be performed at wafer probe prior to separating the individual integrated circuit devices and packaging them for final shipment. Identification of non-functional and marginal devices at this stage avoids the expense of packaging undesirable devices.
Overall cost is a significant factor in the success of integrated circuit products. It is desirable to keep testing costs low, since these add directly to the cost of producing the parts. However, the cost of testing cannot be lowered too far, as doing so comes at the expense of product reliability.
The equipment used for testing integrated circuit devices is relatively expensive. Parametric testers used for wafer probe typically have a limited number of test stations. An example of such a testing apparatus is a Keithley System 350.
One type of test performed on integrated circuit devices at wafer probe is end of life testing. DC voltages are applied to the devices being tested to stress them, followed by measuring parameters such as V.sub.T and transistor gain for test devices provided on the integrated circuit chip. The precise tests performed depend on the nature of the device. All such testing is similar in that stressing voltages are applied to the devices for a relatively long time compared to the time required to perform the parametric tests.
Testing equipment such as the Keithley tester described above is flexible, programmable, and fairly expensive. It is inefficient to use such equipment for the relatively simple tests used in end of life testing. Alternative approaches have been tried, in which devices are stresses separately in equipment designed specifically for this purpose, and then transferred to the more expensive testing equipment for testing. However, this approach has some problems. These include inaccuracies introduced by the handling required. In addition, it has been observed that some of the problems which may occur are partially "healed" as a result of exposure to light. Thus, marginal or defective chips could be tested and scored as passing even though they do not actually satisfy the required test parameters.
It would be desirable to provide a method and apparatus for testing relatively large numbers of integrated circuit devices at wafer level without requiring additional complex equipment. Such method and apparatus should be accurate, efficient, and relative inexpensive.